1. Technical Field
The present invention relates to a communication system between first and second independently clocked devices, for example, first and second chips.
The invention particularly, but not exclusively, relates to a chip-to-chip communication system for a stacked device, i.e., a device comprising at least two chips assembled in a three-dimensional (3D) stacking configuration and the following description is made with reference to this field of application for convenience of explanation only.
2. Description of the Related Art
As it is well known, the development of stacking technology for heterogeneous device integration has recently increased in importance.
Stacking of chips, in which two or more integrated circuits or ICs of different types are placed one on the top of the other in a same package, is an alternative to silicon integration and provides improvements at the system design level in terms of size, cost, speed, power consumption and ease of application for a wide variety of products.
However, a successful implementation of the stacking or 3D technology deals with state-of-the-art of assembly processes such as wafer back-grinding, handling, die attach, wirebond and alignment. So, the choice of a stacking or 3D technology depends largely on the application of the final chip to be obtained.
It should be also emphasized that a correct and enhanced chip-to-chip communication in a stacked device is a fundamental feature to be guaranteed, in particular in the scenario of the so-called Systems-on-Chip and Systems-in-Package.
In this field, synchronization is a key issue for modern integrated systems where the distribution of a global clock signal is not possible or not advisable given the complexity of the systems themselves. In particular, the so-called Globally Asynchronous Locally Synchronous (GALS) approach is important for application to 3D communication systems where clock transmission can be a difficult task at extremely high frequencies but where communication occurs through sampled inter-chip packets.
Asynchronous to synchronous synchronizers and particularly a technique which involves level shifting of a metastable voltage either within a synchronizer stage or between synchronizer stages are described for instance in the U.S. Pat. No. 5,418,407 issued on May 23, 1995 to Frenkil (VLSI Technology Inc.).
Also known from the U.S. Pat. No. 5,256,912 issued on Oct. 26, 1993 to Rios (Sun Microsystems Inc.) is a synchronizer using a plurality of clock signals generated by a specialized clock circuit, in conjunction with synchronizer modules incorporating transparent latches, to synchronize signals passing from a first clock domain to a second clock domain.
Other system and method for synchronizing data are described in the U.S. Pat. Nos. 6,690,203; 7,245,684; 6,711,089; 6,493,819; 6,067,335; and 5,256,912.
These known communication circuits are substantially based on very simple driver models, but require sense-amplifiers and biasing blocks for the generation of internal voltage values, in particular in the receiver. So, these known communication circuits show a great power consumption due to short-circuit currents.
A chip-to-chip vertical communication system, based on contactless IO schemes exploiting capacitive coupling as an inter-chip channel, is shown for instance in FIG. 1. In particular, an upper metal layer of the technology process manufacturing the system is used to form a capacitive channel with the interposition of a dielectric, the chip-to-chip communication system being globally indicated at 1 and hereinafter briefly called the system 1.
As shown in FIG. 1, the system 1 comprises a plurality of communication units 2, each comprising a transmitter 3 and a receiver 4.
In particular, the transmitter 3 resides on a first chip A and the receiver 4 resides on a second chip B, the first and second chips A and B being assembled in a stacked or 3D configuration, the first chip A being on the top of chip B and the transmitter 3 and the receiver 4 being positioned on respective facing surfaces of the chips A and B, more particularly the transmitter 3 on a bottom surface of the chip A and the receiver 4 on a top surface of the chip B, with reference to an XYZ axis-system as shown in FIG. 1. Obviously, the above configuration (transmitter 3-chip A; receiver 4-chip B) is considered only as an example, a reverse configuration (transmitter 3-chip B; receiver 4-chip A) being also possible, the same consideration applying.
It should be emphasized that this approach benefits from on-chip communication circuits able to guarantee high performances, low power dissipation and reliable flexibility in data exchange.
A chip-to-chip communication system, providing precharge and evaluation blocks within a transmitter TX and a receiver RX of the system, such transmitter and receiver having clock signals derived from a common clock signal is also described in the U.S. Patent Application Publication No. 2007/092011, published on Mar. 14, 2007, assigned to STMicroelectronics, Srl, and schematically shown in FIGS. 2A and 2B.
The system 10 comprises the transmitter TX 11 and the receiver RX 12, connected to each other through a connection block 15. The connection block 15 is an inter-chip communication channel.
In particular, the transmitter TX 11 has an output terminal TXout connected to an input terminal RXin of the receiver RX 12 through the connection block 15.
The connection block 15 could be a capacitive connection block, as shown in FIG. 2A or an ohmic connection block, as shown in FIG. 2B.
The transmitter TX 11 also has an input terminal TXin receiving an input or data signal D. In a similar manner, the receiver RX 12 also has an output terminal RXout issuing an output signal Q. In particular, the input data signal D and the output signal Q are n-bit digital signals.
Furthermore, the receiver RX 12 is connected to a first terminal G, the reference G being indifferently used to indicate the terminal or the signal applied thereto, for sake of simplicity of description. In particular, G is the primary clock signal/terminal.
Also, the transmitter TX 11 is connected to a second terminal CP as well as to a third terminal SD, also in this case the references CP and SD being indifferently used to indicate the terminals or the signals applied thereto, for sake of simplicity of description. In particular, CP is the secondary clock signal/terminal and SD is the preset signal/terminal.
The first and second control terminals, G and CP, are connected to each other at the connection block 15 through a first 13 and a second buffer 14.
As already indicated, the transmitter TX 11 is associated with a first chip, conventionally indicated as chip A, referring back to FIG. 1, while the receiver RX 12 is associated to a second chip, conventionally indicated as chip B, the first and second chips, A and B, being assembled in a stacked or 3D configuration.
The primary clock signal G and the secondary clock signal CP are balanced clock trees used to synchronize a bus of the input data signal D. In particular, the primary clock signal G and the secondary clock signal CP are obtained by a same clock signal. In the example shown in FIGS. 2A and 2B, the secondary clock signal CP is the transmitter clock signal which is delayed with respect to the primary clock signal G, which is in turn the receiver clock signal. In this way, the secondary clock signal CP guarantees a correct functional synchronization between the transmitter TX 11 and the receiver RX 12, i.e., between the chips A and B. In order to achieve that, the clock signal is transmitted in the opposite direction of the input data signal D, i.e., from the data receiver chip B to the data transmitter chip A.
So, the input data signal D flows from the first chip A to the second chip B, while the clock signals CP and G flow from the second chip B to the first chip A. In summary, the input data signal D and the clock signals CP and G flow in opposite directions.
Even advantageously under several aspects, also this known system require the definition of a dedicated clock channel apt to make the two chips isochronous and in phase to each other in order to ensure a correct working.